Due to the poor quality of the silicon carbide / silicon dioxide interface realisation and their thin gate oxide layer, SiC MOSFETs are more susceptible to charge trapping mechanisms than silicon MOSFETs. These phenomena are amplified over time, resulting in decreased transistor perfomance and increased losses. To monitor this ageing mechanism, an analog method is proposed to extract a newly discovered health indicator from the gate voltage (VGS) waveform. This is accomplished by slowing down a specific turn-on using a dual-channel active gate driver. The on-line health monitoring method is then experimentally validated on a 1200V-36A SiC MOSFET in both no-load and pulse width modulation (PWM) conditions.